1. Field of the Invention
The present invention relates to a static noise checking technique, which is performed during the design of an integrated circuit such as an LSI (Large Scale Integration). The static noise check is performed after cell arrangement and inter-cell wiring, to carry out noise checking on the cell arrangement/inter-cell wiring.
2. Description of the Related Art
Generally speaking, at design of integrated circuits such as LSIs, cell arrangement and inter-cell wiring are performed, and a noise value that may arise in each wire is calculated and checked. In cases where a noise value exceeding a limit value is caused, (that is, when a noise value error occurs), cell rearrangement and inter-cell rewiring are performed (for example, see Japanese Patent Application Publication Nos. HEI08-278992, HEI10-096762, 2001-217315, 2002-358341).
Referring to FIG. 12A, FIG. 12B, and FIG. 13, a common LSI designing method will be detailed hereinbelow. FIG. 12A and FIG. 12B are views for describing the hierarchical morphology of LSI design; FIG. 13 is a flowchart indicating common LSI designing procedures.
As shown in FIG. 12A and FIG. 12B, during LSI design, the LSI chip 1 is hierarchically organized into three groups: a chip level, a sub-chip level, and an LSG (Layout Sub Group) level. Cell arrangement and inter-cell wiring are performed on the lowest layer of the LSG level. Here, in FIG. 12A, reference character 1a designates a sub chip; reference character 1b, an LSG; reference character 1c, an external I/O area; reference character id, RAM macro in the LSG 1b; reference character 1e, a standard cell in the LSG 1b. 
Such an LSI chip 1 is designed, following the procedures (steps S51 through S59) of FIG. 13. RTL (Register Transfer Level) designing is performed first (step S51), and logic synthesis (step S52) and floor planning cell arrangement (step S53) are then performed. Based on the floor planning, cell arrangement and inter-cell wiring are performed (step S54).
Based on the result of the cell arrangement and inter-cell wiring, static timing analysis is performed (step S55). If any problem (error such as signal delay/racing) in timing is present (YES route of step S56), the process returns to step S54, and cell arrangement and inter-cell wiring are performed once again. If there is no timing problem (NO route of step S56), static noise checking on the result of the cell arrangement and inter-cell wiring is performed (step S57).
In the static noise checking, a noise value is calculated as a degree at which at least one aggressor, which is a wire running in parallel with a victim wire that is to be checked, induces noise onto the victim, and it is evaluated whether or not the noise value exceeds a limit value (step S58). If the noise value exceeds the limit value, it is decided that a noise value error has occurred (YES route of step S58), the process returns to step S54, and the same procedures (steps S54 through S58) are repeated until step S58 makes a NO decision. On the other hand, if the noise value is equal to or smaller than the limit value, it is decided that no noise value error occurs (NO route of step S58), and manufacture data for the LSI chip 1 is produced based on the cell arrangement and the inter-cell wiring (step S59), and the designing of the LSI chip 1 is completed.
In the previous static noise check technique (step S57), a noise value is calculated on the assumption of the most critical (worst) condition, that is, on the assumption of a condition where the victim and the aggressor work concurrently, or a condition where signals are transferred on both of the wires concurrently. The calculated noise value and the limit value are compared, and all the victims in which the noise value exceeds the limit value are recognized as errors.
In actual LSIs, however, it is rare that all the logical cells connected to one wiring branch work concurrently, and some of the logical cells never work concurrently. That is, victims and their aggressors do not always work concurrently.
In spite of this, all the victims whose noise values exceed the limit value are recognized as errors, so that the number of errors is greatly increased, and a great amount of work is needed for correction to ensure error avoidance. In addition, the freedom of layout design is limited, load on DA (Design Automation) is increased, and optimum cell arrangement and inter-cell wiring in the whole of the LSI chip are unavailable.
In particular, due to a great amount of wiring thereof, recent LSIs contain wires running close to and in parallel with each other, even when spacing wiring is performed. Thus, if the foregoing static noise checking is performed, a great amount of noise value error is output.
In view of this disadvantage, a technique has been desired in which victims with no timing problem are excluded from the victims which are decided to have noise value errors. Correction is thus performed only on those wires experiencing actual timing problems, so that the amount of correction for noise value errors can be reduced.